VAL_AI: an integrated debugger tool for post-silicon validation

Abstract

As demands for more complex SoCs becomes high due to several technological advancements, the market for these chips is endless and companies are driven to keep up with the changing times by streamlining their top-down process for a more efficient flow. Post-silicon validation is one of the most important steps during System-on-Chip production process as this happens after fabrication to test functionalities of chips in both nominal conditions and varied process, voltage, and temperature conditions. Post-silicon validation debugging is the last line of defense for all possible attacks and bugs. The process involves rigorous amount of iterative and repeated process of opening several files and comparing data from previous tests. Due to the complicated nature of debugging, there is a need to effectively systematize it and automate the current process of digital validation. Moreover, there are many software tools in the development stages and there is also a need to integrate them altogether. This work first starts with expounding on the current process and tools being used by NXP Semiconductors during post-silicon digital validation. The focus is then driven to automate merging files, visualization of data, and identification of possible causes of failure through a three-step solution: data collection, candidate identification, and problem analysis. The work begins with how the test runs are stored, queried, and shown. Two clustering techniques: kmeans and agglomerative clustering are also discussed. Some dimension reduction techniques like principal component analysis and uniform manifold and approximation projection were also elaborated. These techniques could help development and future work. Application integration is the last step to unify all infant software tools currently in the works under NXP Semiconductors.