dc.contributor.author | Robertsén, Fredrik | |
dc.contributor.author | Westerholm, Jan | |
dc.contributor.author | Mattila, Keijo | |
dc.date.accessioned | 2017-07-31T14:01:12Z | |
dc.date.available | 2017-07-31T14:01:12Z | |
dc.date.issued | 2017 | |
dc.identifier.citation | Robertsén, F., Westerholm, J., & Mattila, K. (2017). Designing a graphics processing unit accelerated petaflop capable lattice Boltzmann solver: Read aligned data layouts and asynchronous communication. <i>International Journal of High Performance Computing Applications</i>, <i>31</i>(3), 246-255. <a href="https://doi.org/10.1177/1094342016658109" target="_blank">https://doi.org/10.1177/1094342016658109</a> | |
dc.identifier.other | CONVID_27057602 | |
dc.identifier.other | TUTKAID_74093 | |
dc.identifier.uri | https://jyx.jyu.fi/handle/123456789/54958 | |
dc.description.abstract | The lattice Boltzmann method is a well-established numerical approach for complex fluid flow simulations. Recently, general-purpose graphics processing units (GPUs) have become available as high-performance computing resources at large scale. We report on designing and implementing a lattice Boltzmann solver for multi-GPU systems that achieves 1.79 PFLOPS performance on 16,384 GPUs. To achieve this performance, we introduce a GPU compatible version of the so-called bundle data layout and eliminate the halo sites in order to improve data access alignment. Furthermore, we make use of the possibility to overlap data transfer between the host central processing unit and the device GPU with computing on the GPU. As a benchmark case, we simulate flow in porous media and measure both strong and weak scaling performance with the emphasis being on large-scale simulations using realistic input data. | |
dc.language.iso | eng | |
dc.publisher | Sage | |
dc.relation.ispartofseries | International Journal of High Performance Computing Applications | |
dc.subject.other | Lattice Boltzmann | |
dc.subject.other | graphics processing unit | |
dc.subject.other | Titan | |
dc.subject.other | asynchronous communication | |
dc.subject.other | memory alignment | |
dc.subject.other | data layout | |
dc.subject.other | large-scale I/O | |
dc.subject.other | load balance | |
dc.title | Designing a graphics processing unit accelerated petaflop capable lattice Boltzmann solver: Read aligned data layouts and asynchronous communication | |
dc.type | article | |
dc.identifier.urn | URN:NBN:fi:jyu-201707193327 | |
dc.contributor.laitos | Fysiikan laitos | fi |
dc.contributor.laitos | Department of Physics | en |
dc.type.uri | http://purl.org/eprint/type/JournalArticle | |
dc.date.updated | 2017-07-19T09:15:03Z | |
dc.type.coar | http://purl.org/coar/resource_type/c_2df8fbb1 | |
dc.description.reviewstatus | peerReviewed | |
dc.format.pagerange | 246-255 | |
dc.relation.issn | 1094-3420 | |
dc.relation.numberinseries | 3 | |
dc.relation.volume | 31 | |
dc.type.version | acceptedVersion | |
dc.rights.copyright | © The Author(s) 2016. This is a final draft version of an article whose final and definitive form has been published by Sage. Published in this repository with the kind permission of the publisher. | |
dc.rights.accesslevel | openAccess | fi |
dc.subject.yso | virtauslaskenta | |
dc.subject.yso | prosessorit | |
jyx.subject.uri | http://www.yso.fi/onto/yso/p21150 | |
jyx.subject.uri | http://www.yso.fi/onto/yso/p10874 | |
dc.relation.doi | 10.1177/1094342016658109 | |
dc.type.okm | A1 | |