Stability of charge-pump phase-locked loops : the hold-in and pull-in ranges
Kuznetsov, N.V., Matveev, A.S., Yuldashev, M.V., Yuldashev, R.V., & Bianchi, G. (2020). Stability of charge-pump phase-locked loops : the hold-in and pull-in ranges. IFAC-PapersOnLine, 53(2), 2022-2026. https://doi.org/10.1016/j.ifacol.2020.12.2511
© Authors, 2020
The problem of design and analysis of synchronization control circuits is a challenging task for many applications: satellite navigation, digital communication, wireless networks, and others. In this article the Charge-Pump Phase-Locked Loop (CP-PLL) electronic circuit, which is used for frequency synthesis and clock generation in computer architectures, is studied. Analysis of CP-PLL is not trivial: full mathematical model, rigorous definitions, and analysis still remain open issues in many respects. This article is devoted to development of a mathematical model, taking into account engineering aspects of the circuit, interpretation of core engineering problems, definition in relation to mathematical model, and rigorous analysis.
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Additional information about fundingThe work is supported by the Russian Science Foundation(project 19-41-02002).
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Harmonic balance analysis of pull-in range and oscillatory behavior of third-order type 2 analog PLLs Kuznetsov, N.V.; Lobachev, M.Y.; Yuldashev, M.V.; Yuldashev, R.V.; Kolumbán, G. (Elsevier, 2020)The most important design parameters of each phase-locked loop (PLL) are the local and global stability properties, and the pull-in range. To extend the pull-in range, engineers often use type 2 PLLs. However, the engineering ...
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