SEGR in SiO2-Si3N4 Stacks
Javanainen, A., Ferlet-Cavrois, V., Bosser, A., Jaatinen, J., Kettunen, H., Muschitiello, M., Pintacuda, F., Rossi, M., Schwank, J. R., Shaneyfelt, M. R., & Virtanen, A. (2014). SEGR in SiO2-Si3N4 Stacks. IEEE transactions on Nuclear Science, 61(4), 1902-1908. https://doi.org/10.1109/TNS.2014.2303493
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IEEE transactions on Nuclear ScienceDate
2014Copyright
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Abstract. This work presents experimental Single Event Gate
Rupture (SEGR) data for Metal–Insulator–Semiconductor (MIS)
devices, where the gate dielectrics are made of stacked SiO2–Si3N4
structures. A semi-empirical model for predicting the
critical gate voltage in these structures under heavy-ion exposure
is first proposed. Then interrelationship between SEGR cross-
section and heavy-ion induced energy deposition probability in
thin dielectric layers is discussed. Qualitative connection between
the energy deposition in the dielectric and the SEGR is proposed.
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Institute of Electrical and Electronics EngineersISSN Search the Publication Forum
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https://converis.jyu.fi/converis/portal/detail/Publication/23827716