Physical implementation workload efficiency improvement

Abstract

EDA workloads on both cloud and on-premises require an understanding of the jobs on the host for the best turnaround time and cost efficiency. A lot of EDA jobs are launched with over demanded compute resources than necessary. They often fail if launched with resources less than what is required, thus increasing turnaround time. It is important to have prior knowledge of resource requirements according to design size and workload nature. This work explores synthesis, floorplan, clock tree synthesis, placement, and routing jobs for a small and bigger Arm CPU core design on compute clusters within the Arm’s existing flow. The jobs dependency in terms of runtime and maximum memory utilization on multi-core jobs are investigated on different AMD and Intel machines on AWS cloud servers. It is found that a small design size does not benefit from parallelism. On the other hand, a bigger design has significantly reduced runtime for the implementation jobs when launched with multi-threaded CPUs. This work provides Arm with a method to extract information on EDA jobs with their flow and a schema that can be used for machine learning models to predict and build optimum job configuration