Delay line design for high-resolution time-to-digital converters

Abstract

Microelectronic technology is constantly scaling towards more modern, advanced, smaller technology nodes, which allows higher operational speeds and more robustness to total ionising dose. However, the technology downscaling also lowers supply voltage, thus shrinking the available headroom for the voltage domain operations. That is why more and more attention is paid to the processing of the analog signal in the time domain, where zero crossings of a signal represent analog information. That is why time-to-digital converters (TDC) take the stage instead of analog-to-digital converters (ADC). Moreover, in order to withstand harsh environments to be able to operate in the field of high energy and nuclear physics and space, these devices have to be able to tolerate the ionising radiation effects, thus, radiation hardening is required to mitigate this degradation caused by these effects. This thesis aims to thoroughly explore the fundamental architectures of TDC, and propose and compare more advanced system architectures for time-to-digital converters, which would allow to improve possible resolution and power consumption (which is the main bottleneck for space applications and battery-powered devices) in comparison to the existing designs. Detailed analysis of the Lee-Kim and Maneatis delay cells is conducted, covering minimal achievable delay, power consumption, the effect of local mismatch on the performance, jitter and supply sensitivity, in two different technologies: UMC 180nm and TSMC 65nm. The performances of the cells have been compared and the best one was chosen for the design of the delay line for precise timing signal generation. The solution for delay cell enhancement to be suitable for specific architectures is given for enabling coarse-fine tuning. The sub-gate delay resolution in the order of pico-seconds is discussed and is achieved by using local passive interpolation, feed-forwarding technique and their combination. Additionally, the final design of a high-speed delay line is discussed, incorporating various improvements to ensure the correct operation of the delay line at high clock frequency in all process corners. The work concludes with a novel approach to mitigating supply sensitivity using active DAC control to amplify and counteract supply fluctuations, ensuring improved performance and reliability.