Precise delay generation using differential-input delay cells used in delay-locked-loop

Abstract

With the advancement of technology, integrated circuits became smaller and faster with ever-decreasing technology nodes. The voltage headroom to work with analog circuits became smaller with the downscaling and it paved the path to process the analog signals in time domain. Time-to-digital converter is that kind of device that can take advantage of processing the signal in time domain with picosecond resolution. A delay-locked-loop (DLL) based TDC uses a delay line which acts as the timing generator. Like a phase-locked-loop (PLL), a DLL is also constituted by a phase detector, charge pump, and voltage-controlled delay line. The number of delay cells in the delay line depends on the total amount of time that needs to be measured. Although an additional counter could act as coarse converter to increase the dynamic range. Every individual cell produces the same amount of delay that defines the resolution of the TDC.

A delay cell can be single-ended which is a current-starved structure or differential-input structure that produces picosecond delay. The delay of every individual cell can be controlled externally by the control voltage. A single-ended buffer can have the advantage of less power consumption, and less area but a differential stage can obviously perform better in terms of noise rejection. High noise and environmental variation immunity is the primary concern for the delay line as it causes output jitter in the timing generator.

This thesis presents the comparison between the two most used differential-input buffer architectures that are used for timing generation in DLL-based TDCs: Maneatis cell and Lee-Kim cell. Maneatis cell is a fully differential architecture where the NMOS tail current source is biased with self-biasing technique. This self-biasing structure omits the requirement to use a different process-independent bandgap reference voltage for the biasing. On the other hand, the Lee-Kim cell is a pseudo-differential architecture with two cross-coupled inverters where both PMOS transistors are current starved. Less voltage headroom requirement, and high output swing can be the aspects by which one can tend to choose Lee-Kim cell as it does not have any tail current source but their performances against process, voltage, and temperature (PVT) variations are worth considering.

This thesis presents how these two delay cell architectures perform in PVT variations and random mismatch. Obviously, for a DLL, an external reference clock is needed which has a frequency in GHz range and requires a PLL. But that is also one aspect which can be seen in the future.