Study of IR-drop induced jitter in high precision timing ASICs

Abstract

The design, testing and manufacturing of application-specific-integrated circuits (ASICs) have become increasingly complex due to large-scale device integration and advancements in technology scaling. Very-large-scale integration (VLSI) has remarkably enhanced electronic circuit performance, impacting profoundly on daily life through various applications such as efficient microprocessors and larger memory chips. Despite these improvements, new challenges have arisen, particularly in designing an efficient power delivery network (PDN) that ensures a stable and evenly distributed power supply across the chip.

The rising integration of VLSI introduces critical challenges for PDN design, leading to power supply noise, voltage drops, and ground bounces, which themselves causes timing degradation, including jitter. High-energy physics (HEP) ASICs are likewise affected by IR drop-induced jitter, significantly limiting the performance of time-critical particle tracking chips. As a result, accurately determining the effects of IR drop induced jitter through short-length simulations has become essential.

To address these challenges, an innovative approach for precisely predicting IR drop induced jitter during the ASIC design phase has been developed. This approach is built on a simulation framework initially created by the experimental physics-electronic systems for experiments-microelectronics (EP-ESE-ME) group at the European organization for nuclear research (CERN). Subsequent development and implementation were conducted under my direct responsibility, focusing on refining, and enhancing its application. The completed framework offers a pre-silicon methodology to estimate IR drop impact on time-interval-error jitter (TIE) within a digital-on-top (DoT) approach. This technique involves correlating real switching activities with accurate dynamic power results for precise analogue timing simulations.

Additionally, this framework builds upon an existing methodology applicable on the commercial Computer Assisted Design (CAD) tools Cadence Innovus, Voltus and Tempus, which is further guided and integrated with Python and Tool Command Language (TCL) scripts to overcome existing limitations. It has been applied on twocurrent ASICs developed at CERN and validated against experimental results where possible.