Effective scheme of parity-preserving-reversible floating-point divider

Abstract

Most recently, there has been a growing need for developing very-large-scale integration (VLSI) circuits with low energy consumption and high speed for use in fast transmission systems. In addition, the main challenge in designing irreversible integrated circuits is heat generation due to data loss. Thus, in recent years, reversible design has been preferred for low-power VLSI circuits because the data are not lost. In this article, a new design of parity-preserving-reversible (PPR) floating-point divider is suggested. A floating-point divider structure includes parallel adder, multiplexer, register, and left-shift register. To optimize these circuits, first, we propose a 5 × 5 PPR block and a PPR D-latch. Second, using the proposed circuits, a ripple-carry-adder, a register, and an efficient parallel-input-parallel-output-left-shift register, rounding-register, and normalization register circuits are introduced in PPR logic. The comparisons illustrate that the suggested circuits are preferable to the circuits presented in previous works in terms of various criteria such as quantum cost, constant inputs, and garbage outputs.