Synthesis of phase-locked loop : analytical methods and simulation

dc.contributor.author	Yuldashev, Renat
dc.date.accessioned	2013-12-10T07:30:30Z
dc.date.available	2013-12-10T07:30:30Z
dc.date.issued	2013
dc.identifier.isbn	978-951-39-5490-1
dc.identifier.other	oai:jykdok.linneanet.fi:1288747
dc.identifier.uri	https://jyx.jyu.fi/handle/123456789/42622
dc.format.extent	1 verkkoaineisto (50 sivua)
dc.language.iso	eng
dc.publisher	University of Jyväskylä
dc.relation.ispartofseries	Jyväskylä studies in computing
dc.rights	In Copyright
dc.subject.other	vaihelukitut silmukat
dc.subject.other	vaihevertailijat
dc.subject.other	phase-locked loop
dc.subject.other	phase detector
dc.subject.other	characteristic
dc.subject.other	PLL with squarer
dc.title	Synthesis of phase-locked loop : analytical methods and simulation
dc.type	doctoral thesis
dc.identifier.urn	URN:ISBN:978-951-39-5490-1
dc.type.dcmitype	Text	en
dc.type.ontasot	Väitöskirja	fi
dc.type.ontasot	Doctoral dissertation	en
dc.contributor.tiedekunta	Informaatioteknologian tiedekunta	fi
dc.contributor.tiedekunta	Faculty of Information Technology	en
dc.contributor.yliopisto	University of Jyväskylä	en
dc.contributor.yliopisto	Jyväskylän yliopisto	fi
dc.contributor.oppiaine	Tietotekniikka	fi
dc.type.coar	http://purl.org/coar/resource_type/c_db06
dc.relation.issn	1456-5390
dc.relation.numberinseries	175
dc.rights.accesslevel	openAccess
dc.type.publication	doctoralThesis
dc.subject.yso	elektroniset piirit
dc.subject.yso	matemaattiset mallit
dc.subject.yso	simulointi
dc.rights.url	https://rightsstatements.org/page/InC/1.0/

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