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dc.contributor.advisorLeroux, Paul
dc.contributor.advisorPanseri, Luigi
dc.contributor.advisorDoucet, Stephan
dc.contributor.advisorPigeard, Bertrand
dc.contributor.authorBHOSALE, YOGESH
dc.date.accessioned2024-09-27T05:26:07Z
dc.date.available2024-09-27T05:26:07Z
dc.date.issued2024
dc.identifier.urihttps://jyx.jyu.fi/handle/123456789/97277
dc.description.abstractA Proportional To Absolute Temperature (PTAT) current source is designed in 22 nm CMOS process technology while emphasizing on power consumption, temperature coefficient, line sensitivity, PSRR, and noise performance. The analysis of power consumption across varying supply voltage from 1 V to 1.4 V and temperatures ranging from -40 °C to 120 °C shows the efficiency and stability of the iptat current (PTAT source) and the ibias, the iref current from the ISRC (current source) block. This PTAT current source generates 16.08 A of the iptat current and consumes 67 W power at 1.2 V supply, at room temperature (27 °C). The ISRC block generates the iout, ibias and iref currents. The temperature coefficient of the iptat current is determined, and it has a temperature coefficient of 3.78 kppm/°C. The iout (output current) current of 2 kppm/°C temperature coefficient is obtained by adding the ibias current with the iptat current in specific proportion, which is then further used for driver of Bluetooth transmitter. After the line sensitivity analysis, the iptat current indicates the lowest sensitivity to supply voltage variation of 0.28 %/V, whereas the iout current is the most sensitive with line sensitivity of 0.99 %/V. The noise analysis is done over the frequency range of 10 Hz to 1 GHz, also the PSRR analysis showed a that the iptat current possesses the PSRR of 50 dB at 100 kHz. A Monte Carlo simulation involving 1000 runs quantifies the mismatch variations in key parameters, with 3σ variation of a 4.9 % mismatch observed for the iout current and a 3σ variation of a 6.1 % mismatch for the iptat current. These findings underscore the importance of robust design methodologies to minimize mismatch and enhance circuit reliability.en
dc.format.extent45
dc.language.isoen
dc.subject.otherPTAT current source
dc.subject.otherreference current
dc.subject.otherbias current
dc.subject.otherresistor trimming
dc.titleA 67 μW, 1.2 V, low area 22-nm CMOS PTAT bias reference current source
dc.identifier.urnURN:NBN:fi:jyu-202409276152
dc.type.ontasotMaster’s thesisen
dc.type.ontasotPro gradu -tutkielmafi
dc.contributor.tiedekuntaMatemaattis-luonnontieteellinen tiedekuntafi
dc.contributor.tiedekuntaFaculty of Sciencesen
dc.contributor.laitosFysiikan laitosfi
dc.contributor.laitosDepartment of Physicsen
dc.contributor.yliopistoJyväskylän yliopistofi
dc.contributor.yliopistoUniversity of Jyväskyläen
dc.contributor.oppiaineSoveltava fysiikkafi
dc.contributor.oppiaineApplied Physicsen
dc.rights.copyrightJulkaisu on tekijänoikeussäännösten alainen. Teosta voi lukea ja tulostaa henkilökohtaista käyttöä varten. Käyttö kaupallisiin tarkoituksiin on kielletty.fi
dc.rights.copyrightThis publication is copyrighted. You may download, display and print it for Your own personal use. Commercial use is prohibited.en
dc.contributor.oppiainekoodi4023
dc.subject.ysolämpötila
dc.subject.ysosähkötekniikka
dc.subject.ysotemperature
dc.subject.ysoelectrical engineering


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