Time interleaved SAR ADC

Abstract

Several ADC architectures are found to exist such as Successive Approximation Register, pipeline, sigma-delta, flash etc. The choice of these architectures depends on the required sampling frequency and resolution of the application. ADCs are known to be an essential interface between the analog world and digital computer data. Due to this key function, ADC circuits have been thoroughly studied for over 4 decades, addressing numerous associated challenges. However, a new type of ADCs has recently emerged, capturing significant attention. These are high-speed time-interleaved ADCs (TI ADCs), typically ranging from 1 GS/s to over 50 GS/s, generally fabricated using CMOS process with low to medium resolution ranging from 6 to 12 bits. Even though, these ADCs can be utilized in high-speed electronic measurement devices and radar systems, their latest emphasis is driven by the next generation 100 Gbps/500 Gbps fiber optic transceivers. These transceivers use high speed ADCs and DSPs (Digital-Signal-Processors) to achieve ultra-fast data communication across long-haul networks (connecting cities, oceans and continents), metro networks (connecting enterprises within metropolitan regions) and data centers (interconnecting infrastructure within data centers). Owing to its outstanding power efficiency, the TI SAR ADC has been known as a preferred solution at such high sampling rates. However, this architecture encounters challenges associated with channel mismatches. The three major categories of mismatches include an offset mismatch, gain and a timing mismatch. The initial part of this thesis focuses on developing a MATLAB model to analyze the inherent mismatches found in time interleaved ADCs, which can adversely affect their overall performance. The MATLAB model plays a vital role for simulating these mismatches, offering valuable understanding about their effect on the overall functionality of time-interleaved ADCs. As technology evolves and the system requirements become more demanding, the high speed ADCs are constantly pushed to their performance limits. A major challenge in ADC design encountered in wearable computing machines is that they need ultra-low power consumption combined with increasing the sampling rate demands of modern communication systems. After operational amplifiers, comparators are recognized to be the second most commonly used electronic component and play a significant part in ADCs by sampling and transforming input signals into digital equivalents. The speed of ADCs depends on a comparator’s decision-making response time. Ultra-deep submicron (UDSM) CMOS technology introduces additional complications since devices are required to be operational at lower supply voltages. In contrast, threshold voltages have not scaled down proportionally. As a result, designing high-speed, low power and low noise comparators becomes exceptionally problematic, specifically under low voltage conditions. Additionally, a limited common-mode input range occurs from the low-voltage operation, which is vital for maintaining the effective performance of high-speed ADC architectures. As compared to typical comparators, dynamic comparators are remarkably more power-efficient. There are diverse architectures for dynamic comparators. The primary focus of this thesis will be the high-speed, low power Strong-Arm Latch comparator for Time-Interleaved SAR ADCs. Initially, the Strong-Arm Latch Comparator was simulated (RC Extracted) using 28-nm bulk CMOS and was then ported to 22-nm FD-SOI technology. A layout was subsequently carried out in this 22-nm FD-SOI technology. An inclusive comparison (RC Extracted) was then iii conducted between these two versions and numerous existing comparators. A Figure of Merit (FOM) was computed to facilitate this comparison, and the Strong-Arm Latch Comparator was evaluated based on its speed, noise and energy per cycle.