Dielectrophoresis as an assembly method for carbon nanotube memory elements

Abstract

The experiments described in this Master's thesis aim to assess the practicality of using dielectrophoresis (DEP) for assembling memory elements from carbon nanotubes (CNTs). These elements were field-effect transistors (FETs) with a wide hysteresis window. The devices assessed were made on a silicon substrate with a HfO2 - TiO2 - HfO2 gate dielectric layer to ensure a predictable hysteresis for memory operation. The FETs were used for further research in regard to environmental effects in their operation. An average yield of 12.5 % over 26 different trapping attempts, a total of 650 gaps, was achieved for single trapped CNTs in a two-electrode configuration with a 1 µm gap between electrodes with a width of 300 nm. The electrical parameters for DEP (f = 300 kHz, VPP = 5 V, t = 2 min) were consistent in the batch, but the CNT mass concentration of the 1,2-dichloroethane suspension varied between 1/98000 and 1/270000. 47 successful FETs with hysteresis were produced in the 350 devices evaluated by electrical measurements. Trapping the nanotubes exclusively on electrode tips was not possible with the configuration used in the experiments. Additionally, controlling the concentration of CNTs in the suspension was difficult. This resulted in unpredictable amounts of material between different samples as well as separate gaps between electrodes in the same sample. Because surfactants weren't used, the widespread attachment of the CNTs to each other also posed a problem. The FET operation testing was hampered by current leaks through the gate dielectric. The devices that were produced also had a relatively high current in the off-state, which resulted in low on/off ratios for the CNTFETs.