Exact lock-in range for classical phase-locked loops
Julkaistu sarjassa
JYU DissertationsTekijät
Päivämäärä
2021Tekijänoikeudet
© The Author & University of Jyväskylä
Phase-locked loops (PLLs) are are widely used in various applications: Wireless communications, GPS navigation, gyroscope systems, computer architectures, electrical grids, and others. PLLs are inherently non-linear, but in engineering practice, they are actually designed and analyzed mostly using linear methods. Recent development in the manufacturing of electronics has led to ever higher
operating frequencies and, hence, to more stringent requirements for the design of PLLs.
This dissertation is devoted to the study of phase-locked loops, in particular to their synchronization properties. The ability of the phase-locked loop to synchronize fast without cycle slipping is characterized by the loop’s lock-in range. The problem of determining the lock-in range is called the Gardner problem for lock-in range, named after IEEE Fellow F. M. Gardner, who formulated the
problem in the 1960s. Mathematically rigorous formulation of the lock-in range by N. Kuznetsov, however, is only a few years old, and the first approaches to improve the estimates of the lock-in range using non-linear methods were proposed by K.D. Aleksandrov in his doctoral dissertation.
This work furthers the mathematically rigorous study of the lock-in range and is devoted to the exact calculation of the lock-in in range for a classical phase-locked loop with active proportionally integrating and lead-lag filters. For phase space, phase-locked loop models with piecewise-linear phase detectors characteristized by an exact lock-in range is obtained for both the considered filter types. For the phase-space phase-locked loop model with an active proportionally integrating filter and tangential that is characteristic of a phase detector, the lock-in range is proven to be infinite. All theorems have strict mathematical proof and have been confirmed by numeric simulation.
Keywords: PLL, phase-locked loops, lock-in range, Gardner problem, exact lock-in range
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Julkaisija
Jyväskylän yliopistoISBN
978-951-39-8953-8ISSN Hae Julkaisufoorumista
2489-9003Julkaisuun sisältyy osajulkaisuja
- Artikkeli I: Kuznetsov, N.V., Arseniev, D.G. Blagov, M.V., Wei, Z. Lobachev, M. Y., Yuldashev, M. V., Yuldashev, R.V. (2022). The Gardner problem and cycle slipping bifurcation for type 2 phase-locked loops. International Journal of Bifurcation and Chaos. Accepted.
- Artikkeli II: Blagov, M. V., Kuznetsov, N. V., Lobachev, M. Y., Yuldashev, M. V., Yuldashev, R. V. (2021). The conservative lock-in range for PLL with lead-lag filter and triangular phase detector characteristic. Preprint
- Artikkeli III: Blagov, M. V., Kuznetsova, O. A., Kudryashov, E. V., Kuznetsov, N., Mokaev, T. N., Mokaev, R. N., Yuldashev, M. V., & Yuldashev, R. V. (2019). Hold-in, Pull-in and Lock-in Ranges for Phase-locked Loop with Tangential Characteristic of the Phase Detector. In A. Diveev, I. Zelinka, F. L. Pereira, & E. Nikulchev (Eds.), INTELS ’18 : Proceedings of the 13th International Symposium “Intelligent Systems" (pp. 558-566). Elsevier. Procedia Computer Science, 150. DOI: 10.1016/j.procs.2019.02.093
- Artikkeli IV: Blagov, M. V., Kudryashova, E. V., Kuznetsov, N., Leonov, G. A., Yuldashev, M. V., & Yuldashev, R. V. (2016). Computation of lock-in range for classic PLL with lead-lag filter and impulse signals. In H. Nijmeijer (Ed.), 6th IFAC Workshop on Periodic Control Systems PSYCO 2016 (pp. 42-44). International Federation of Automatic Control (IFAC). IFAC Proceedings Volumes (IFAC-PapersOnline), 49. DOI: 10.1016/j.ifacol.2016.07.972
- Artikkeli V: Blagov, M. V., Kuznetsov, N., Leonov, G. A., Yuldashev, M. V., & Yuldashev, R. V. (2015). Simulation of PLL with impulse signals in MATLAB: Limitations, hidden oscillations, and pull-in range. In ICUMT 2015 : Proceedings of the 7th International Congress on Ultra Modern Telecommunications and Control Systems and Workshops (pp. 85-90). Institute of Electrical and Electronic Engineers. International Conference on Ultra Modern Telecommunications & workshops. DOI: 10.1109/ICUMT.2015.7382410
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Computation of lock-in range for classic PLL with lead-lag filter and impulse signals
Blagov, M. V.; Kudryashova, E. V.; Kuznetsov, Nikolay; Leonov, Gennady A.; Yuldashev, Marat V.; Yuldashev, Renat V. (International Federation of Automatic Control (IFAC), 2016)For a classic PLL with square waveform signals and lead-lag filter for all possible parameters lock-in range is computed and corresponding diagrams are given. -
Hold-in, Pull-in and Lock-in Ranges for Phase-locked Loop with Tangential Characteristic of the Phase Detector
Blagov, M. V.; Kuznetsova, O. A.; Kudryashov, E. V.; Kuznetsov, Nikolay; Mokaev, T. N.; Mokaev, R. N.; Yuldashev, M. V.; Yuldashev, R. V. (Elsevier, 2019)In the present paper the phase-locked loop (PLL), an electric circuit widely used in telecommunications and computer architectures is considered. A new modification of the PLL with tangential phase detector characteristic ... -
О проблеме Гарднера для систем управления фазовой автоподстройкой частоты
Kuznetsov, N.V.; Lobachev, M.Y.; Yuldashev, M.V.; Yuldashev, R.V. (Russian Academy of Sciences, 2019)This report shows the possibilities of solving the Gardner problem of determining the lock-in range for multidimensional phase-locked loops systems. The development of analogs of classical stability criteria for the ... -
The Egan problem on the pull-in range of type 2 PLLs
Kuznetsov, Nikolay V.; Lobachev, Mikhail Y.; Yuldashev, Marat V.; Yuldashev, Renat V. (Institute of Electrical and Electronics Engineers (IEEE), 2021)In 1981, famous engineer William F. Egan conjectured that a higher-order type 2 PLL with an infinite hold-in range also has an infinite pull-in range, and supported his conjecture with some third-order PLL implementations. ... -
Harmonic balance analysis of pull-in range and oscillatory behavior of third-order type 2 analog PLLs
Kuznetsov, N.V.; Lobachev, M.Y.; Yuldashev, M.V.; Yuldashev, R.V.; Kolumbán, G. (Elsevier, 2020)The most important design parameters of each phase-locked loop (PLL) are the local and global stability properties, and the pull-in range. To extend the pull-in range, engineers often use type 2 PLLs. However, the engineering ...
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