SEGR in SiO2-Si3N4 Stacks
Abstract
Abstract. This work presents experimental Single Event Gate
Rupture (SEGR) data for Metal–Insulator–Semiconductor (MIS)
devices, where the gate dielectrics are made of stacked SiO2–Si3N4
structures. A semi-empirical model for predicting the
critical gate voltage in these structures under heavy-ion exposure
is first proposed. Then interrelationship between SEGR cross-
section and heavy-ion induced energy deposition probability in
thin dielectric layers is discussed. Qualitative connection between
the energy deposition in the dielectric and the SEGR is proposed.
Main Authors
Format
Articles
Research article
Published
2014
Series
Subjects
Publication in research information system
Publisher
Institute of Electrical and Electronics Engineers
The permanent address of the publication
https://urn.fi/URN:NBN:fi:jyu-201409132790Use this for linking
Review status
Peer reviewed
ISSN
0018-9499
DOI
https://doi.org/10.1109/TNS.2014.2303493
Language
English
Published in
IEEE transactions on Nuclear Science
Citation
- Javanainen, A., Ferlet-Cavrois, V., Bosser, A., Jaatinen, J., Kettunen, H., Muschitiello, M., Pintacuda, F., Rossi, M., Schwank, J. R., Shaneyfelt, M. R., & Virtanen, A. (2014). SEGR in SiO2-Si3N4 Stacks. IEEE transactions on Nuclear Science, 61(4), 1902-1908. https://doi.org/10.1109/TNS.2014.2303493
License
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