SEGR in SiO2-Si3N4 Stacks
Javanainen, A., Ferlet-Cavrois, V., Bosser, A., Jaatinen, J., Kettunen, H., Muschitiello, M., . . . Virtanen, A. (2014). SEGR in SiO2-Si3N4 Stacks. IEEE transactions on Nuclear Science, 61 (4), 1902-1908. doi:10.1109/TNS.2014.2303493
Published inIEEE transactions on Nuclear Science
© 2014 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.
Abstract. This work presents experimental Single Event Gate Rupture (SEGR) data for Metal–Insulator–Semiconductor (MIS) devices, where the gate dielectrics are made of stacked SiO2–Si3N4 structures. A semi-empirical model for predicting the critical gate voltage in these structures under heavy-ion exposure is first proposed. Then interrelationship between SEGR cross- section and heavy-ion induced energy deposition probability in thin dielectric layers is discussed. Qualitative connection between the energy deposition in the dielectric and the SEGR is proposed.